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d a t a sh eet product speci?cation file under integrated circuits, ic02 october 1988 integrated circuits tda8425 hi-fi stereo audio processor; i 2 c-bus
october 1988 2 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 general description the tda8425 is a monolithic bipolar integrated stereo sound circuit with a loudspeaker channel facility, digitally controlled via the i 2 c-bus for application in hi-fi audio and television sound. feature: source and mode selector for two stereo channels pseudo stereo, spatial stereo, linear stereo and forced mono switch volume and balance control bass, treble and mute control power supply with power-on reset quick reference data package outline 20-lead dual in-line; plastic (sot146); sot146-1; 1996 november 26. parameter symbol min. typ. max. unit supply voltage (pin 4) v cc 10.8 12.0 13.2 v input signal handling v l 2 -- v input sensitivity full power at the output stage v i - 300 - mv signal plus noise-to-noise ratio (s+n)/n - 86 - db total harmonic distortion thd - 0.05 - % channel separation a- 80 - db volume control range g - 64 - 6db treble control range g - 12 - 12 db bass control range g - 12 - 15 db
october 1988 3 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 fig.1 block diagram.
october 1988 4 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 pinning functional description source selector the input to channel 1 (ch1) and channel 2 (ch2) is determined by the source selector. the selection is made from the following af input signals: in 1 l (pin 18); in1 r (pin 20) or in2 l (pin 1); in2 r (pin 3) mode selector the mode selector selects between stereo, sound a and sound b (in the event of bilingual transmission) for out r and out l. volume control and balance the volume control consists of two stages (left and right). in each part the gain can be adjusted between +6 db and - 64 db in steps of 2 db. an additional step allows an attenuation of 3 80 db. both parts can be controlled independently over the whole range, which allows the balance to be varied by controlling the volume of left and right output channels. linear stereo, pseudo stereo, spatial stereo and forced mono mode (1) it is possible to select four modes: linear stereo, pseudo stereo, spatial stereo or forced mono. the pseudo stereo mode handles mono transmissions, the spatial stereo mode handles stereo transmissions and the forced mono can be used in the event of stereo signals. (1) during forced mono mode the pseudo stereo mode cannot be used. fig.2 pinning diagram.
october 1988 5 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 bass control the bass control stage can be switched from an emphasis of 15 db to an attenuation of 12 db for low frequencies in steps of 3 db. treble control the treble control stage can be switched from +12 db to - 12 db in steps of 3 db. bias and power supply the tda8425 includes a bias and power supply stage, which generates a voltage of 0.5 v cc with a low output impedance and injector currents for the logic part. power-on reset the on-chip power-on reset circuit sets the mute bit to active, which mutes both parts of the treble amplifier. the muting can be switched by transmission of the mute bit. i 2 c-bus receiver and data handling bus specification the tda8425 is controlled via the 2-wire i 2 c-bus by a microcomputer. the two wires (sda - serial data, scl - serial clock) carry information between the devices connected to the bus. both sda and scl are bidirectional lines, connected to a positive supply voltage via a pull up resistor. when the bus is free both lines are high. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low. the set up and hold times are specified in ac characteristics. a high-to-low transition of the sda line while scl is high is defined as a start condition. a low-to-high transition of the sda line while scl is high is defined as a stop condition. the bus receiver will be reset by the reception of a start condition. the bus is considered to be busy after the start condition. the bus is considered to be free again after a stop condition. module address data transmission to the tda8425 starts with the module address mad. fig.3 tda8425 module address.
october 1988 6 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 subaddress after the module address byte a second byte is used to select the following functions: volume left, volume right, bass, treble and switch functions the subaddress sad is stored within the tda8425. table 1 defines the coding of the second byte after the module address mad. table 1 second byte after module address mad the automatic increment feature of the slave address enables a quick slave receiver initialization, within one transmission, by the i 2 c-bus controller (see fig.5). de?nition of 3rd byte a third byte is used to transmit data to the tda8425. table 2 defines the coding of the third byte after module address mad and subaddress sad. table 2 third byte after module address mad and subaddress sad function 128 64 32 16 8 4 2 1 msb lsb 76543210 volume left 0 0 0 0 0 0 0 0 volume right 0 0 0 0 0 0 0 1 bass 0 0 0 0 0 0 1 0 treble 0 0 0 0 0 0 1 1 switch functions 0 0 0 0 1 0 0 0 subaddress sad function msb lsb 76543210 volume left vl 1 1 v05 v04 v03 v02 v01 v00 volume right vr 1 1 v15 v14 v13 v12 v11 v10 bass ba 1 1 1 1 ba3 ba2 ba1 ba0 treble tr 1 1 1 1 tr3 tr2 tr1 tr0 switch functions s1 1 1 mu efl stl ml1 ml0 is
october 1988 7 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 truth tables truth tables for the switch functions table 3 source selector table 4 pseudo stereo/spatial stereo/linear stereo/forced mono table 5 mute notes 1. pseudo stereo function is not possible in this mode. 2. where: por = power-on reset. truth tables for the volume, bass and treble controls table 6 volume control function ml1 ml0 is channel stereo 1 1 0 1 stereo 1 1 1 2 sound a 0 1 0 1 sound b 1 0 0 1 sound a 0 1 1 2 sound b 1 0 1 2 choice stl efl spatial stereo 1 1 linear stereo 1 0 pseudo stereo 0 1 forced mono (1) 00 mute mu active; automatic after por (2) 1 not active 0 2 db/step (db) v 5v 4v 3v 2v 1v 0 6 1 1 1111 4 1 1 1110 - 62 0 1 1101 - 64 0 1 1100 - 80 0 1 1011 - 80 0 0 0000
october 1988 8 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 table 7 bass control table 8 treble control 3 db/step (db) ba3 ba2 ba2 ba0 15 1111 15 1011 12 1010 0 0110 - 12 0010 - 12 0000 3 db/step (db) tr3 tr2 tr2 tr0 12 1111 12 1010 0 0110 - 12 0010 - 12 0000
october 1988 9 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 sequence of data transmission after a power-on reset all five functions have to be adjusted with five data transmissions. it is recommended that data information for switch functions are transmitted last because all functions have to be adjusted when the muting is switched off. the sequence of transmission of other data information is not critical. the order of data transmission is shown in figures 4 and 6. the number of data transmissions is unrestricted but before each data byte the module address mad and the correct subaddress sad is required. fig.4 data transmission after a power-on reset. fig.5 data transmission after a power-on reset with auto increment. fig.6 data transmission except after power-on reset.
october 1988 10 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 ratings limiting values in accordance with the absolute maximum system (iec 134) note 1. human body model: c = 100 pf, r = 1.5 k w and v 3 4 kv; charge device model: c = 200 pf, r = 0 w and v 3 500 v. dc characteristics v cc = 12 v; t amb =25 c; unless otherwise speci?ed parameter symbol min. max. unit supply voltage v cc 016v voltage range for pins with external capacitors v cap 0v cc v voltage range for pins 11 and 12 v sda, scl 0v cc v voltage range at pins 1, 3, 9, 11, 12, 13, 18 and 20 v i/o 0v cc v output current at pins 9 and 13 i o - 45 ma total power dissipation at t amb < 70 cp tot - 450 mw operating ambient temperature range t amb 070 c storage temperature range t stg - 25 +150 c electrostatic handling, classi?cation a (1) parameter symbol min. typ. max. unit supply voltage v cc 10.8 12.0 13.2 v supply current at v cc = 12 v i cc - 26 35 ma internal reference voltage v ref 5.4 0.5 v cc 6.6 v internal voltage at pins 1, 3, 18 and 20 dc voltage internally generated; capacitive coupling recommended v l - v ref - v internal voltage at pins 9 and 13 v o - v ref - v sda; scl (pins 11 and 12) input voltage high v ih 3.0 - v cc v input voltage low v il - 0.3 - 1.5 v input current high i ih -- +10 m a input current low i il - 10 --m a output voltage at pins with external capacitors pins 6 to 8, 14 to 17, 19, v cap.n - v ref - v pin 2 v cap.2 - v cc - 0.3 - v
october 1988 11 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 ac characteristics (1) v cc = 12 v; bass/treble in linear position; pseudo and spatial stereo off; r l > 10 k w ; c l < 1000 pf; t amb =25 c; unless otherwise speci?ed parameter symbol min. typ. max. unit i 2 c bus timing (see fig.7) sda, scl (pin 11 and 12) clock frequency range f scl 0 - 100 khz the high period of the clock t high 4 --m s the low period of the clock t low 4.7 --m s scl rise time t r -- 1 m s scl fall time t f -- 0.3 m s set-up time for start condition t su; sta 4.7 --m s hold time for start condition t hd; sta 4 --m s set-up time for stop condition t su; sto 4.7 --m s time bus must be free before a new transmission can start t buf 4.7 --m s set-up time data t su; dat 250 -- ns inputs in1 l (pin 18) in1 r (pin 20); in2 l (pin 1) in2 r (pin 3) input signal handling (rms value) at v u = - 12 db; thd 0.5% v i(rms) 2 -- v input resistance r i 20 30 40 k w frequency response ( - 0,5 db) bass and treble in linear position; stereo mode; effects off f 20 - 20 000 hz outputs out r (pin 9); out l (pin 13) output voltage range (rms value) at thd 0.7%; v i(max) 2 v v o(rms) 0.6 -- v load resistance r l 10 -- k w output impedance z o -- 100 w signal plus noise-to-noise ratio (weighted according to ccir 468-2); v o = 600 mv gain = 6 db (s+n)/n - 78 - db gain = 0 db (s+n)/n - 86 - db gain = - 20 db (s+n)/n - 68 - db crosstalk between inputs at gain = 0 db; 1 khz; opposite inputs grounded (50 w ); in1l (pin 18) to in2l (pin1) or in1r (pin 20) to in2r (pin 3) a cr - 100 - db
october 1988 12 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 total harmonic distortion (f = 20 hz to 12.5 khz) for v i(rms) = 0.3 v; gain = +6 db to - 40 db thd - 0.05 - % for v i(rms) = 0.6 v; gain = 0 db to - 40 db thd - 0.07 0.4 % for v i(rms) = 2.0 v; gain = - 12 db to - 40 db thd - 0.1 - % channel separation at 10 khz gain = 0 db a cs - 80 - db ripple rejection (gain = 0 db; bass and treble in linear position) f ripple = 100 hz rr 100 - 50 - db crosstalk attenuation from logic inputs to af outputs (gain = 0 db; bass and treble in linear position) a l - 100 - db volume control for truth table see table 6 control range at f = 1 khz (36 steps) maximum voltage gain (6 db step) g max 56 - db minimum voltage gain ( - 64 db step) g min - 63 - 64 - db mute position g mute - 80 - 90 - db gain tracking error; balance in mid-position g -- 2db step resolution gain from 6 db to - 40 db g step 1.5 2.0 2.5 db/step gain from - 42 db to - 64 db g step 1.0 2.0 3.0 db/step treble control for truth table see table 8 control range for c 8-5 ; c 14-5 = 5.6 nf maximum emphasis at 15 khz with respect to linear position g 11 12 13 db maximum attenuation at 15 khz with respect to linear position g 11 12 13 db resolution g step 2.5 3.0 3.5 db/step parameter symbol min. typ. max. unit
october 1988 13 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 note to the ac characteristics 1. balance is realized via software by different volume settings in both channels (left and right). bass control for truth table see table 7 control range for c 6-7 ; c 15-16 = 33 nf maximum emphasis at 40 hz with respect to linear position g 14 15 16 db maximum attenuation at 40 hz with respect to linear position g 11 12 13 db resolution g step 2.5 3.0 3.5 db/step spatial and pseudo function spatial: antiphase crosstalk a- 52 - % pseudo: phase shift (see fig.8) parameter symbol min. typ. max. unit fig.7 timing requirements for i 2 c-bus. t su; sta = start code set-up time. t hd; sta = start code hold time. t su; sto = stop code set-up time. t buf = bus free time. t su; dat = data set-up time. t hd; dat = data hold time.
october 1988 14 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 fig.8 pseudo (phase in degrees) as a function of frequency (left output). curve pin 17 (nf) pin 19 (nf) effect 1 15 15 normal 2 5.6 47 intensi?ed 3 5.6 68 more intensi?ed fig.9 input signal handling capability; gain = - 10 db; r s = 600 w ; r l = 10k w ; bass/treble = 0 db; v cc = 12 v.
october 1988 15 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 fig.10 input signal handling capability plotted against gain setting; thd = - 60 db; f = 1 khz; r s = 600 w ; r l = 10 k w ; bass/treble = 0 db; v cc = 12 v. fig.11 output signal handling capability; gain = 6 db; r s = 600 w ; r l = 10 k w , bass/treble = 0 db, v cc = 12 v.
october 1988 16 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 fig.12 source selector separation (channel 2 and channel 1); gain = 0 db; v i1 = 0 v; v i2 = 1 v, r s =0 w ; r l = 10 k w ; bass/treble = 0 db; v cc = 12 v. fig.13 stereo channel separation as a function of frequency; r s =0 w , r l = 10 k w ; bass/treble = 0 db; v cc = 12 v. (1) gain = 0 db; v i = 1.0 v. (2) gain = 6 db; v i = 0.5 v.
october 1988 17 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 fig.14 mute signal rejection as a function of frequency; gain = 0 db; v i = 1.0 v; r s =0 w ; r l = 10 k w ; bass/treble = 0 db; v cc = 12 v. fig.15 ripple rejection as a function of frequency; voltage ripple = 0.3 v (rms); r s =0 w ; r l = 10 k w ; bass/treble = 0 db; v cc = 12 v.
october 1988 18 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 fig.16 noise output voltage as a function of gain; weighted ccir468 quasi peak gain, + 6 db to - 64 db; v i = 0 v, r s =0 w ; r l = 10 k w ; bass/treble = 0 db; v cc = 12 v. fig.17 frequency response of bass and treble control; bass and treble gain settings = - 12 to +15 db; gain is 0 db; v i = 0.1 v; r s9 = 600 w ; r l = 10 k w ; v cc = 12 v.
october 1988 19 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 fig.18 tone control with t-filter. fig.19 tone control.
october 1988 20 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 fig.20 turn-on behaviour; c = 2.2 m f; r l = 10 k w . fig.21 turn-off behaviour; without modulation. fig.22 turn-off behaviour; with modulation (shaded area).
october 1988 21 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 fig.23 turn-on/off power supply circuit diagram. i cc =25ma i load = 239 ma t on =15ms t off = 110 ms fig.24 level diagram.
october 1988 22 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 fig.25 test and application circuit diagram.
october 1988 23 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 package outline unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot146-1 92-11-17 95-05-24 a min. a max. b z max. w m e e 1 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 6.40 6.22 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 2.0 4.2 0.51 3.2 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 0.25 0.24 0.14 0.12 0.01 0.10 0.30 0.32 0.31 0.39 0.33 0.078 0.17 0.020 0.13 sc603 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 20 1 11 10 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) (1) dip20: plastic dual in-line package; 20 leads (300 mil) sot146-1
october 1988 24 philips semiconductors product speci?cation hi-? stereo audio processor; i 2 c-bus tda8425 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.

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